A) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, a semiconductor wafer and a semiconductor device, and more particularly to a method for fabricating a semiconductor device having a multilayer wiring structure, a semiconductor wafer and a semiconductor device.
B) Description of the Related Art
In fabricating a semiconductor integrated circuit device, a number of chip areas divided by a scribe area are defined in a semiconductor wafer. Semiconductor elements are formed in each chip area, and an interconnection or wiring layer and an interlayer insulating layer are alternately stacked in each chip area. After the semiconductor integrated circuit structure is formed in each chip area, the semiconductor wafer is diced in the scribe area to separate each chip. Dicing is executed through chipping which dices the whole thickness of a semiconductor wafer with a dicing saw.
The scribe area is not used as an area for circuits. Although position alignment marks and a test element group are formed in some area of the scribe area, the other area has the exposed surface of the semiconductor wafer, along which the wafer is diced. The diced plane of each semiconductor chip has concave/convex surfaces like bur.
Japanese patent Laid-open Publication No. HEI-4-282852 proposes to dice a semiconductor wafer at a position between narrow insulating layers formed on both sides of a center line of a scribe area. The Publication describes that the insulating layer is harder than semiconductor so that concave/convex surfaces of the diced plane are prevented from extending over the scribe area and entering the chip.
Dicing a semiconductor water with a dicing saw poses sometimes the problem that the uppermost insulating layer of a semiconductor chip is wound around the dicing saw and cracked or peeled off, resulting in partial exposure of wirings and electrodes, electric short, corrosion and the like. Japanese Patent Laid-open Publication No. HEI-9-199449 proposes to form a crack preventive groove in the uppermost insulating layer.
FIG. 22A shows the structure of a crack preventive groove disclosed in Japanese Patent Laid-open Publication No. HEI-9-199449. Semiconductor elements are formed on the surface of a silicon substrate 101, and an interlayer insulating film 102 is formed thereon. A wiring 110 is formed on the interlayer insulting film 102, and another interlayer insulating film 104 is formed. A bonding pad 113 is formed being connected to the wiring 110. The uppermost insulating layer 105 and a polyimide protective layer 107 are formed, the uppermost insulating layer 105 being a silicon oxide layer or a lamination layer of a silicon oxide layer and a silicon nitride layer. At the same time when etching the protective layer 107 and insulating layer 105 to expose the surface of the bonding pad 113, a crack preventive groove 108 is formed through the protective layer 107 and insulating layer 105. Even if the protective layer 107 and insulating layer 105 are wound around a dicing saw at the chip end plane and cracked, this crack is stopped at the crack preventive groove 108.
In order to improve the integration degree and operation speed of a semiconductor integrated circuit device, constituent semiconductor elements are made finer. The finer the semiconductor elements, a higher resolution is required for an exposure process and an aperture ratio becomes larger and a depth of focus becomes shallower. In order to focus an image at a shallow depth of focus, an underlying layer of resist is desired to be flat. A planarizing process such as chemical mechanical polishing (CMP) is often used.
Japanese Patent Laid-open Publication No. HEI-10-335333 discloses an integrated circuit using wirings of W or AI and teaches that even if a wiring is formed and thereafter an interlayer insulating film is formed and CMP is performed, the surface cannot be planarized perfectly, and that the wiring intervals are set within a constant range, e.g., from the narrowest to twice the narrowest, at the maximum, in order to planarize the surface of the interlayer insulating film. By disposing dummy wirings not only in the chip area but also in the scribe area, it becomes possible to form an insulating layer having a flat surface in the whole area of a wafer.
FIG. 22B shows an example of the structure of a semiconductor devices having dummy wirings disposed in a chip area and in the whole scribe area, disclosed in Japanese Patent Laid-open Publication No. HEI-10-335333. In FIG. 22B, a pad-peripheral circuit area B is shown in the right area and a scribe area A is shown in the left area.
In the surface layer of a silicon substrate 101, an element isolation region 103 is formed by shallow trench isolation (STI). A gate insulating film and a gate electrode are formed on an active region of the silicon substrate, to form a MOS transistor. At the same time, a wiring 106 of the same material as that of the gate electrode is also formed on the element isolation region 103. An interlayer insulating film 109 is formed covering the gate electrode 109.
A wiring layer having wirings 110 and dummy wirings 111 is formed on the interlayer insulating film 109. The dummy wirings 111 are disposed not only in the pad-peripheral circuit area B but also in the scribe area A. The wiring layers 110 and 111 are covered with an interlayer insulating film 112 having a planarized surface. Similarly, wirings 114 and dummy wirings 115 are formed on the interlayer insulating film 112, and covered with an interlayer insulating film 116 having a planarized surface. Wirings 117 and dummy wirings 118 are formed on the interlayer insulating film 116 and covered with an interlayer insulating film 119. Wirings 120 and dummy wirings 121 are formed on the interlayer insulating film 119 and covered with an interlayer insulating film 122.
The uppermost wiring layer including a pad 113 and wirings 123 is formed on the interlayer insulating film 122, and covered with a cover layer constituted of an insulating layer 124 and a passivation layer 125. The surface of the pad 113 is exposed by selectively etching the passivation layer 125 and insulating layer 124.
The above-cited Publication describes that this structure can planarize perfectly the whole surface of a wafer.